Compiler and CMP Codesign

 

PIs: Alex K. Jones, Rami Melhem, and Sangyeun Cho

Multi-core computing, where several processor cores are combined together into a single chip, has become the standard in computer processor design. In effect, each chip has become a small parallel computer and leveraging the processing power of parallel computing efficiently is a difficult challenge. Parallel computing attempts to accelerate computational tasks by separating the work into segments that can be calculated independently using different processors. Unfortunately, these processors need to communicate with each other to complete the computational tasks correctly. This communication and the resulting access to data are major limiting factors to how much a computational task can be accelerated with multiple processors.

This research proposes a cooperatively designed system that considers the method for storing and accessing data (memory), the method for communication between processors (network), the software that controls how programs are executed (operating system), and the design of the program executables themselves (compilation) to maximize the program execution speed. The key observation is that while each component of the system can be improved independently, each component contains information that can help the other components to realize even greater benefits. Just as a transportation infrastructure requires information about traffic patterns; for example, if traffic patterns were ignored and if highways connect rural areas and only side streets connect major cities, traffic would reach a standstill while highways are inefficiently used. Likewise, the communication network cannot be efficiently designed without information from programs on communication patterns.

The outcomes from this project will be the development of cross-layer design concepts for multi-core computer architectures that will result in performance improvements and effective use of more processor cores within a single chip.


This project is supported by the National Science Foundation.


Related Publications

  1. •Y. Li, Y. Chen, A. K. Jones, Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching, Workshop on Emerging Supercomputing Technologies, 2011..


  3. •A. Abousamra, A. K. Jones, R. Melhem, Two-hop free-space based optical interconnects for Chip Multiprocessors, Proc. of NOCS, May 2011.


  1. •A. Abousamra, A. K. Jones, R. Melhem, NoC-Aware Cache Design for Multithreaded Execution on Tiled Chip Multiprocessors, Proc. of High Performance and Embedded Architectures and Compilers (HiPEAC), Jan. 2011.


  3. •Y. Li, A. Abousamra, R. Melhem, A. K. Jones, Compiler-assisted Data Distribution for Chip Multiprocessors Categories and Subject Descriptors, ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.


  1. •C. Ihrig, R. Melhem, and A. K. Jones, Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip Multiprocessors, Design Automation Conference (DAC), 2010.


  1. •Y. Li, R. Melhem, and A. K. Jones, Compiler-based Data Classification for Hybrid Caching, Proceedings of the ASPLOS Workshop on the Interaction between Compilers and Computer Architectures (INTERACT), 2010.


  1. •A. Abousamra, R. Melhem, A. K. Jones, Winning with Pinning in NoC, IEEE Hot Intercon- nects (HOTI), 2009.


  1. •S. Shao, A. K. Jones, and R. Melhem, Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems, IEEE Transactions for Parallel and Distributed Systems (TPDS), Vol. 20, No. 3, pp. 331-345.