ECE351 Digital Systems DesignECE351 Digital Systems DesignECE 351 for the Spring 2014 semester has been officially ended. In the following, please find the final project demos from some of the student groups of this course. Enjoy!
Snake game on FPGA
Alarm system design
Instructor
- Dr. Wei Gao
- Lectures: TR 9:40am-10:55am, 405 Min Kao
- Office hours: TR 11:00am - 12:00pm, 302 Min Kao
- Email: weigao (at) utk (dot) edu (please replace (at) with @ and (dot) with .)
- Phone: 865-974-3984
Course Materials
Textbook - The Designer's Guide to VHDL
- Author: Peter J. Ashenden
- Publisher: Morgan Kaufmann; 3rd edition
- Schedule
- Course policies
Lab: 224 Min kao
Lab hours: TBD
Teaching Assistant
- Wenchao Cao (wcao2@utk.edu)
- TA will help students solve lab and programming problems
Grading
- Lab: 15% (3 labs)
- Course project: 40%. Proposal: 5%, midterm presentation: 10%, final presentation: 10%, final report 15%
- Midterm exam: 15%.
- Final exam: 25%.
- Participation: 5% .